Method for optimization of logic circuits for routability improvement

ABSTRACT

Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design. 
     Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis and produces more predictable implementations which give better routability and yield.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No.10/780,140 filed on Feb. 17, 2004, which is incorporated by referenceherein in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to circuits and, more particularly, toelectronic circuit design.

2. Description of the Related Art

A major goal in the design of Very Large Scale Integration (“VLSI”)chips and other integrated circuits is to combine logic synthesismethods with physical design optimization methods to meet timing, area,and other design objectives of the chip. Physical design optimizationmethods include methods for placement and methods for routing. Logicsynthesis methods determine the type and connectivity of circuits usedto implement the functionality of the chip. Placement methods assign andalter the physical locations of the circuits on the chip. Routingmethods modify the physical path and wire type of the connectionsbetween the circuits.

As the size of the VLSI chip grows, the problem of design closureincreases correspondingly at a geometric rate. Design closure is theprocess of getting a chip design ready to be submitted formanufacturing. Design closure ensures that timing along all paths in thecircuit operate at least as fast as some pre-defined speed in thepresence of various electrical interactions, such as capacitivecoupling. During this process, locations are selected for all of thecomponents making up the design, and those components are connected orrouted with some wiring resources.

A key design parameter that affects design closure significantly isroutability of the circuit. The routability of the circuit is ameasurement of the relative ease of making appropriate connections onthe chip implementing the design. In some cases, this may be impossibleto do; that is, the chip is said to be unroutable. However, when it ispossible, the relative ease of making appropriate connections on thechip implementing the design is measured by the density of wiringresources that is required per unit area of the chip. This densitymeasurement describes the wiring congestion on the chip. Routability (orwiring congestion) affects the performance, noise sensitivity, yield,area, and power of the design.

Two of the steps in the design closure process which are relevant hereare logic synthesis and physical design. Logic synthesis transforms atextual representation of the design into a boolean representation, andmaps the boolean representation down onto circuits and connections. Thecircuits and connections are the basic building blocks in which thephysical design operates. Physical design takes the circuits and assignsthem physical locations on the chip for implementing the design. Thelogical connections are converted into physical connections taking theform of wires and accompanying wiring paths between the connectedelements.

Logical synthesis comprises two optimization stages: (1) a technologyindependent stage and (2) a technology dependent stage. Optimizations ofthe technology independent stage are independent on the type oftechnology that will be used to implement the design. On the other hand,optimizations of the technology dependent stage are dependent on thetype of technology that will be used to implement the design. Each ofthese stages are comprised of a one or more optimization steps. Theapplication of one of these steps is known as a transformation ortransform

The technology independent stage comprises transforming a registertransfer level textual description of the design into a set of booleanequations. The set of boolean equations are then optimized for a set ofgiven metrics such that they will, at the completion of all the steps inthe full synthesis process including technology mapping and physicalsynthesis, lead to a good implementation for delay, area and power.Because the technology independent stage does not know the exacttechnological components that will be associated with the booleanequations, the optimizations in this stage must use measurements ormetrics based on the equations to approximate the area and delay of theentire set of equations. The area is approximated with a literal count,which is a measure of the number of connections or edges in a graphrepresenting all of the boolean equations. For example, assume a set ofboolean equations for an output A would be of the form X=A and B, B=Cand D. Here the literal count is 4 since the number of connections are4. The connection between area and literal count is directlyproportional, meaning that each literal is assumed to consume somepositive, finite, yet unknown, amount of area. The technologyindependent optimizations attempt to minimize the amount of area thatwill be consumed by the equations because smaller implementations aremore likely to fit within the area defined by a chip.

The delay of the design is approximated in the technology independentphase of logic synthesis by a number of levels in the boolean equation.A set of logic equations comprising a set of input signals and outputsignals may be represented by a graph with nodes (which represent gates)and edges (which represent connections) between the inputs and outputs.The paths between inputs and outputs comprises gates and connectionsencountered during a traversal of the graph from input to output. Eachpath comprises gates and connections. The number of levels for an outputsignal in the equation is the maximum number of connections from anygiven input signal to the output signal. There is a directlyproportional relationship between delay and number of levels, meaningthat each level is assumed to consume a positive and finite, yetunknown, amount of delay. The technology independent optimizationsattempt to minimize the amount of delay that will be consumed by theequations because faster implementations are more likely to achievedesign closure.

While the technology independent synthesis optimizations attempt tomeasure the size and speed of the circuit, no metrics exist to determinewhere the literals will be placed or how many wiring paths will want tofollow similar routes, which correlates strongly with the routability ofthe design. So while the basic structure of the design implementation isdefined by the form of the boolean equations at the end of thetechnology independent optimization phase, no attempt has been made tomeasure the wiring characteristics of the design.

The second stage of logic synthesis, which generally follows thetechnology independent optimization stage, is the technology dependentstage. In this stage, the boolean equations are mapped onto a set ofgates that exist in some predefined technology specific library. Thismapping has both logical and electrical components. The logicalcomponent says that all logic described in the boolean equations must bemapped to one or more gates, while the electrical component ensures thatthe electrical characteristics of the gate are not violated and that thedesired speed of the design can be achieved. An example of an electricalcharacteristic is as follows: the amplitude of the signal transmittedfrom one gate is sufficiently large to cause a reaction when received bya connected gates. The strength of these transmitted signals alsodetermines the speed at which the design will operate. This mapping togates is done within the structure defined by the boolean equationscoming out of the technology independent optimization stage of logicsynthesis.

After this technology dependent mapping to gates has been completed, thephysical design process can begin. Physical design consists of two maincomponents, placement and routing. During placement, locations on a chipare assigned for each of the gates coming out of the technologydependent optimization phase of logic synthesis. Based on thisplacement, routing then creates physical wires between the connectedgates. It is not until the locations of the gates are assigned that evena crude approximation can be made about the routability of the design.While delay receives attention early in the design process, if all ofthe connections between the design components cannot be made, the designcannot be implemented. Poor routability of the design also createslonger wires in the design, causing a degradation in timing. If theinability to route the design or the inability to meet timing due topoor routability is discovered only during the physical design process,a designer must return to the technology independent logic synthesisphase to alter the way the design was optimized. However, since thoseoptimizations have no concept of a routability metric, it is difficultto direct those optimizations toward a criteria that cannot be measured.

Physical design information is generally not available early in thelogic synthesis stage. Therefore, existing optimizations andtransformations in the logic synthesis stage, which are primarilytargeted towards timing and area, generally do not consider their impacton routability. Significant decisions regarding the circuit structureare made early in logic synthesis such as during the technologyindependent logic optimization step. Optimizations in this step use aliteral count as a metric for optimization, and, therefore, do notadequately capture the intrinsic entanglement of the circuit. Twocircuit design models with identical literal counts may havesignificantly different routability characteristics after physicaldesign.

It is widely acknowledged that current electronic design automation mustbe able to handle the challenges and opportunities of finer-featuredfabrication processes. These processes are fundamentally premised on theprinciple of separation of concerns in which a complex design flow isserialized into a sequence of manageable steps that are loosely coupled.In this scenario, decisions made in the early stages of design flowbecome binding constraints on later stages. Such serializationpotentially gives less optimal designs than a process thatsimultaneously considers all design aspects. This is unavoidable,however, due to the practical infeasibility of concurrent optimizationof all design parameters, and is deemed acceptable as long as theconstraints that are fed forward by one step to the next can be met. Theprocess breaks down, however, when these constraints becomeunsatisfiable (e.g., the chip becomes unroutable, and falls short of theexpected yield). The typical action in such cases is to go back to theearlier steps and iterate through the steps so as to revisit earlierdesign stages to change suspected problematic decisions. Such iterationhas become particularly necessary between the logic synthesis andplacement steps.

Ideally, the time-wasting iteration between logic synthesis andplacement in today's design methodologies could be eliminated by fusingthese stages to simultaneously optimize the logical structure as wellthe spatial placement of a circuit.

Steps in technology dependent logic synthesis and placement have beencombined to produce a wide variety of methods. Techniques which optimizeboth the logical and physical characteristics are referred to asphysical synthesis. Although, there is work in the area of physicalsynthesis that combines later stages of logic synthesis with placement,the early stages of logic synthesis are not adequately integrated withplacement.

Wire planning evaluates the placement characteristics of circuits duringlogic synthesis and approaches the same problem from a different angle.The wire planning approach assumes that the locations of pins at theboundary of the region being optimized are known. Constraints aregenerated from placement models and synthesis is performed using theconstraints. Although the locations of chip/partition Inputs/Outputs aretypically available, assumptions about locations for pins surroundingthe small region consisting of a few gates in which local optimizations(e.g., factorizations) are being performed is generally difficult topreserve during full chip placement.

Furthermore, statistical interconnect prediction methods (e.g., Rent'srule) do not distinguish between two networks which have the same numberof connections. Interconnect estimates are based primarily on the numberof circuits and IOs. Therefore, they are unsuitable as predictors forroutability optimization during technology independent synthesis.

SUMMARY OF THE INVENTION

In one embodiment of the present invention, a method of optimizing acircuit design model during logic synthesis is provided. The methodcomprises creating a structural metric prior to physical design, thestructural metric being proportional to the routability of the circuitdesign model after the physical design; and using the structural metricduring logic synthesis to create an optimized circuit design model.

In another embodiment of the present invention, machine-readable mediumhaving instructions stored thereon for optimizing a circuit design modelduring logic synthesis is provided. The instructions comprise the stepsof creating a structural metric prior to physical design, the structuralmetric being proportional to the routability of the circuit design modelafter the physical design, and using the structural metric during logicsynthesis to create an optimized circuit design model.

In yet another embodiment of the present invention, a system foroptimizing a circuit design model during logic synthesis is provided.The system comprises means for creating a structural metric prior tophysical design, the structural metric being proportional to theroutability of the circuit design model after the physical design; andmeans for using the structural metric during logic synthesis to createan optimized circuit design model.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIG. 1 shows a flow diagram of a prior art circuit design process;

FIG. 2 shows a flow diagram of a structural logic design process, inaccordance with one embodiment of the present invention;

FIG. 3A shows a flow diagram of the prior art technology independentsynthesis of FIG. 1, followed by technology mapping and buffering;

FIG. 3B shows a flow diagram of the structural technology independentsynthesis of FIG. 2, followed by structural technology mapping andstructural buffering, in accordance with one embodiment of the presentinvention;

FIG. 4A shows a buffer tree constructed using the prior art buffering ofFIG. 3A;

FIG. 4B shows a buffer tree constructed using the structural bufferingof FIG. 3B, in accordance with one embodiment of the present invention;

FIG. 5 shows a flow diagram of an incremental structural metric process,in accordance with one embodiment of the present invention;

FIG. 6A shows an exemplary diagram of a graph representation of adesign;

FIG. 6B shows the diagram of a graph representation of a design of FIG.6A optimized with the prior art design process of FIGS. 1A and 1B;

FIG. 6C shows the diagram of a graph representation of a design of FIG.6A optimized with the structure design process of FIGS. 2A and 2B;

FIG. 7A shows a layout of a carry lookahead adder, illustrating astructural metric, in accordance with one embodiment of the presentinvention;

FIG. 7B shows a layout of a ripple carry adder, illustrating astructural metric, in accordance with one embodiment of the presentinvention; and

FIG. 8 shows an exemplary plot of the average neighborhood size over allcircuits in the design for the carry lookahead adder of FIG. 7A and theripple carry adder of FIG. 7B.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Illustrative embodiments of the invention are described below. In theinterest of clarity, not all features of an actual implementation aredescribed in this specification. It will of course be appreciated thatin the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and are herein described in detail. It shouldbe understood, however, that the description herein of specificembodiments is not intended to limit the invention to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives falling within the spiritand scope of the invention as defined by the appended claims.

It is to be understood that the systems and methods described herein maybe implemented in various forms of hardware, software, firmware, specialpurpose processors, or a combination thereof. In particular, the presentinvention is preferably implemented as an application comprising programinstructions that are tangibly embodied on one or more program storagedevices (e.g., hard disk, magnetic floppy disk, RAM, ROM, CD ROM, etc.)and executable by any device or machine comprising suitablearchitecture, such as a general purpose digital computer having aprocessor, memory, and input/output interfaces. It is to be furtherunderstood that, because some of the constituent system components andprocess steps depicted in the accompanying Figures are preferablyimplemented in software, the connections between system modules (or thelogic flow of method steps) may differ depending upon the manner inwhich the present invention is programmed. Given the teachers herein,one of ordinary skill in the related art will be able to contemplatethese and similar implementations of the present invention.

Routability (or wiring congestion) in a VLSI chip is becomingincreasingly important as chip complexity increases. Congestion has asignificant impact on performance, yield, and chip area. The presentinvention targets the optimization of congestion early in technologyindependent synthesis prior to physical design.

Instead of attempting to optimize the logic structure as well as thespatial placement of a circuit, we pose a more modest goal ofoptimization to the scope of logic synthesis. That is, we propose anaggressive optimization approach that is cognizant of circuit structureduring technology independent synthesis and produces more predictableimplementations which give better routability and yield.

One known method of improving routability is by reducing congestionbased on placement models during the technology independent optimizationphase of logic synthesis. This method typically uses placement models ormakes assumptions regarding placement. The present invention, on theother hand, explores whether routability can be predicted and reduced inthe technology independent phase without making any assumptions aboutplacement. This is important because it is generally difficult to ensurethat placement assumptions made in such prior art methods during thetechnology independent optimization stage can be realized duringplacement.

In the present invention, we propose metrics based only on the networkgraph that can predict congestion characteristics during optimizationearly in the design flow. The metric is based on the connectivity of thenetwork graph implementing the logic function. It does not requireconstraint generation from placement models of the blocks and the use ofsuch constraints in synthesis.

The structure, as measured by one or more of the metrics defined in thisinvention, of a circuit contributes significantly to the wiringcongestion. We perform a prediction-based analysis at the early stagesof logic synthesis, evaluating topological properties of the evolvingcircuit prior to its physical layout. By estimating circuit structureearly in the design flow, we maintain the separation of concernsprinciple, while moderating costly optimizations at the later stage ofphysical synthesis.

The present invention includes an incremental structural metric process.The structural metric is initially computed on the entire logic networkbefore any optimization is performed. During optimization, anincremental recalculation is performed on the design. The incrementalengine tracks all the nodes affected by the changes to the design madeby a given optimization. When change to the design is considered, themethod checks to see if any of the nodes affected by the change havebeen invalidated by the structural analysis engine. If the cost metricon any of these nodes is invalid, then the cost is recomputed for thesenodes. If the cost metric is valid, it is used in computing the cost ofthe proposed change. The change is then applied if the cost improves.Once the change is applied, the nodes affected by these changes aremarked as invalid for the structural metric. Therefore, in thisincremental structure analysis engine, recomputation is performed onlyas needed during optimization. Different structural cost measures may becomputed by the incremental structure analysis engine. Among thechoices, three different structural measures are described asembodiments. Additional structural metrics are possible and are coveredwithin the scope of this invention.

The structural measures topological relationships in different circuitparts known as their adhesion. One structural measure is referred hereinas a distance metric. The design is first represented as a graph withthe circuits represented as nodes and the connections between themrepresented as edges. The distance metric applied to this graph, uses aconcept of neighborhood population that is computed relative to a givencircuit, and to a given distance k measured as graph-theoretic length ofa shortest path between two nodes. For a given circuit c and distance kthe neighborhood population is a set of circuits residing within k nodesaway from c. The average neighborhood population at distance k iscomputed for a set of circuits, and is taken as the cumulative sum oftheir neighborhood population sizes divided by the total number ofconsidered circuits. In general, large average neighborhoods for smallvalues of k suggest that circuit topology is more entangled, and istherefore more likely to produce congested regions during its layout. Inone embodiment of the invention, the method would query the distancemetric from the incremental structural analysis engine and implementoptimizations on the design that reduces average neighborhoods forsmaller values of k.

Another structural measure is the sum of all pairs min-cuts (“SAPMC”) ofthe graph derived from the design. The process to obtaining the graph isidentical to the process for the distance metric. To compute the SAPMC,the minimum number of edges cut in the graph to separate every pair ofnodes in the graph are computed. This number for each pair of node iscalled the min-cut. The sum of the min-cuts for every pair of nodes inthe graph is referred to as the SAPMC. In another embodiment of theinvention, the method would query the SAPMC metric from the incrementalstructural analysis engine and implement optimizations on the design thetotal value of SAPMC.

A third structural measure is the shared expansion metric. First a graphfor the design is obtained. The process to obtaining the graph isidentical to the process for the distance metric. For each pairs ofnodes, the number of shared nodes encountered at a distance k iscomputed The sum over all pairs of nodes for a given set of k values ofshared nodes is known as the expansion of the design. In yet anotherembodiment of the invention, the method would query the expansion metricfrom the incremental structural analysis engine and implementoptimizations on the design based on the expansion metric.

During technology independent optimization in this invention,transformations may propose a set of changes in the circuit designmodel. These changes are proposed as alternatives to the circuits in aregion of the circuit design model based on boolean analysis of theregion of the logic network. The cost of applying each change to thelogic network is evaluated using the incremental structural metricprocess. The proposed change that yields the most improvement in cost isselected and applied.

For example, consider a kernel factoring algorithm. A traditional kernelfactoring optimization identifies circuits or regions of the logicdesign that may be shared. In performing sharing, it would use as a costmetric the total number of literals or connections in the design tominimize. The structure driven kernel factoring would similarly identifycircuits or regions of the logic design that may be shared, but it woulddo so to improve one of the structural metric costs. It would consider apossible sharing optimization. It would query the improvement in thestructural cost metric if that sharing optimization were applied. If thestructural cost improves, it would apply that optimization. If not, theoptimization would continue to consider new opportunities for sharingcircuits and evaluate them. In a similar fashion, decomposition,traditional technology mapping and buffering techniques are modified tooperate with a structural optimization metric.

FIG. 1A shows a prior art design process 100. The design process 100performs (at 105) logic synthesis. The input to the art design processis a register transfer level textual description of the design. Theprocess optimizes the design for both boolean and physicalcharacteristics and produces as output an design with circuits that areplaced and mapped to technology gates from a standard cell library. Asshown in FIG. 1, performing (at 105) the technology independentsynthesis comprises determining (at 110) a literal count metric and anumber of levels metric, which are used to evaluate the quality of thedesign. Referring now to FIG. 3A, performing (at 105) the technologyindependent synthesis further comprises performing (at 305) a kernelfactoring, performing (at 310) a decomposition. The technologyindependent synthesis is followed by performing (at 315) a tech mapping,and performing (at 320) a buffering. It should be understood that thepresent invention is not limited to the transforms of kernel factoringand decomposition, tech mapping, and buffering. Other technologyindependent transforms may be used, as is contemplated by those skilledin the art.

Referring again to FIG. 1A, a technology dependent and physicalsynthesis is performed (at 115), which optimizes wire length androutability, as well as other metrics, such as timing and area. It isdetermined (at 120) whether the design is routable. It is alsodetermined if the timing of the design is met. If the design is notroutable or the timing goals of the design are not met because ofroutability, the design process 100 is repeated and a technologyindependent synthesis is performed (at 105) again. If the design isroutable, a the design is sent to manufacturing.

FIG. 2 shows a structural design process 200, in accordance with oneembodiment of the present invention. The structural design process 200introduces a novel step of performing (at 205) a structural technologyindependent synthesis. As shown in FIG. 2, performing (at 205) thestructural technology independent synthesis comprises determining (at210) a structural metric, in addition to determining a literal countmetric and a number of levels metric. The structural metric may bedetermined (at 210) in an incremental fashion. The structural metric maybe any one of SAPMC (“sum of al-pairs min-cut”), distance, etc. Asdescribed in greater detail below, an incremental structural metriccomputation process is performed (at 215).

Referring now to FIG. 3B, performing (at 205) the structural technologyindependent synthesis further comprises performing (at 405) astructure-driven kernel factoring, performing (at 410) astructure-driven decomposition. The structural technology independentsynthesis if followed by performing (at 415) a structure-driven techmapping, and performing (at 420) a structure-aware buffering. It shouldbe understood that the present invention is not limited to thestructural transforms of structure-driven kernel factoring,structure-driven decomposition, structure-driven tech mapping, andstructure-aware buffering. Other structural technology independenttransforms may be used, as is contemplated by those skilled in the art.

FIG. 4A shows a buffer tree 500 feeding into two cones of logic 505,510, shown as triangular cones. The buffer tree 500 was constructed byperforming (at 320) traditional buffering, as shown in FIG. 3A. FIG. 4Bshows a buffer tree 600 that was constructed by performing (at 420) thestructure-aware buffering technique feeding into the same two cones oflogic 505, 510.

FIG. 5 shows an incremental structure metric process 700 for determininga structural metric using a lazy evaluation technique, as shown in FIG.2B. When a design is entered, the structural metric for all circuits inthe design are determined (at 705). Design changes for time, area,and/or structure are proposed (at 710). It is determined (at 715)whether the structural metrics on the circuits that are affected by thedesign changes are valid. If they are valid, it is determined (at 720)if the design changes provide a cost improvement to the structuralmetric. If so, then the design changes are applied (at 725) to thedesign. If the structural metrics on the affected circuits are invalid,the affected circuits are updated (at 730) incrementally for thestructural metrics. The structural metrics on the circuits affected bythe change are invalidated (at 725). The incremental structural metricprocess 700 then re-proposes (at 710) new changes.

FIG. 6A shows a graph representation of a design. Each node represents acircuit and each edge represents a connection between two of thecircuits. An optimized design using prior art, as illustrated in FIGS.1A and 1B, is shown in FIG. 6B. The optimized design using thestructural method, as illustrated in FIGS. 2A and 2B, is shown in FIG.6C. Although both 6B and 6C have the same number of circuits, it isapparent that the design in FIG. 6C is improved for routability.

FIGS. 7A and 7B show two example circuit design models to illustrate thedistance metric, in accordance with one embodiment of the presentinvention. FIG. 7A shows the schematic of a carry lookahead adder(hereinafter “CLA adder”) and FIG. 7B shows a ripple carry adder. Foreach circuit in the design, neighbors are computed at distances 1, 2, 3,and so on for both adders. Referring now to FIG. 8, the averageneighborhood size over all circuits in the design are plotted for boththe ripple carry adder and the CLA adder. The CLA adder has moreneighbors at smaller distances, while the ripple carry adder has a widerspread of neighborhood. The difference in structural metrics of the twoadders correspond well with their routability characteristics.

As follows from the plotted curves of FIG. 8, the carry-lookaheadstructure has a significantly larger neighborhood population for almostall of its distances compared to ripple-carry structure. Such comparisonis consistent with the fact that ripple-carry adder produces better foryield layouts. In general, during circuit restructuring the objective isto minimize the neighborhood population numbers for smaller values ofdistance k, while allowing their increase for larger distances. Suchoptimization reduces congestion at the immediate vicinity of a change,and distributes it across the extended neighborhood.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. Furthermore, no limitations are intended to thedetails of construction or design herein shown, other than as describedin the claims below. It is therefore evident that the particularembodiments disclosed above may be altered or modified and all suchvariations are considered within the scope and spirit of the invention.Accordingly, the protection sought herein is as set forth in the claimsbelow.

1. A method for optimizing a circuit design, the method comprising:receiving a graph of the circuit design, wherein circuit elements of thecircuit design are nodes in the graph, and connections between thecircuit elements are edges between the nodes; determining a structuralmetric from a structural characteristic of the graph; and performing atechnology-independent logical synthesis to predict wiring congestion onthe circuit design using the structural metric to generate an optimizedcircuit design with a reduced wiring congestion.
 2. The method of claim1, wherein determining the structural metric comprises: determining aplurality of distances, wherein each distance is between each pair ofthe nodes; determining a neighborhood population for each distance,wherein the neighborhood population corresponds to the number of thenodes that are within the distance; and setting the structural metric toan average of the neighborhood populations.
 3. The method of claim 1,wherein determining the structural metric comprises: determining theminimum number of the edges that must be cut to separate every pair ofthe nodes in the graph; and setting the structural metric to the sum ofthe minimum number of edges for each pair.
 4. The method of claim 1,wherein determining the structural metric comprises: determining foreach pair of the nodes, a number of the nodes that are shared within apredefined distance; and setting the structural metric to sum of thenumbers.
 5. The method of claim 1, wherein performing atechnology-independent logical synthesis on the circuit design using thestructural metric to generate an optimized circuit design comprisesusing the structural metric during a technology mapping stage of thelogic synthesis.
 6. The method of claim 1, wherein performing atechnology-independent logical synthesis on the circuit design using thestructural metric to generate an optimized circuit design comprisesusing the structural metric during a buffering stage of the logicsynthesis.
 7. The method of claim 1, further comprising incrementallyupdating the structural metric when logic changes are made to thecircuit design.
 8. A method for optimizing a circuit design, comprising:receiving a register transfer level (RTL) textual description of acircuit design model; generating a graph from the RTL, wherein nodes ofthe graph correspond to circuit elements in the RTL, and edges of thegraph correspond to connections between the circuit elements;determining a structural metric based on a structural characteristic ofthe graph; and optimizing the RTL using a count of the number of nodesin the graph, a count of the number of levels in the graph, and thestructural metric.
 9. The method of claim 8, wherein the optimizing isperformed independently of the type of technology of the circuitelements.
 10. The method of claim 9, further comprising performingtechnology dependent logical synthesis on a result of the optimization.11. The method of claim 10, further comprising performing physicalsynthesis on a result of the technology dependent synthesis.
 12. Themethod of claim 11, further comprising determining whether a result ofperforming the physical synthesis is routable.
 13. The method of claim8, wherein determining the structural metric comprises: determining aplurality of distances, wherein each distance is between each pair ofthe nodes; determining a neighborhood population for each distance,wherein the neighborhood population corresponds to the number of thenodes that are within the distance; and setting the structural metric toan average of the neighborhood populations.
 14. The method of claim 8,wherein determining the structural metric comprises: determining theminimum number of the edges that must be cut to separate every pair ofthe nodes in the graph; and setting the structural metric to the sum ofthe minimum number of edges for each pair.
 15. The method of claim 8,wherein determining the structural metric comprises: determining foreach pair of the nodes, a number of the nodes that are shared within apredefined distance; and setting the structural metric to sum of thenumbers.
 16. A method for optimizing a circuit design, the methodcomprising: receiving a graph of the circuit design, where circuitelements of the circuit design are nodes in the graph, and connectionsbetween the circuit elements are edges between the nodes; determining astructural metric for all the nodes in the graph from a structuralcharacteristic of the graph; selecting at least one of a timing, area,or structural change to the circuit design; determining whether thestructural metrics are still valid based on the change; and implementingthe change to the circuit design upon determining that the changeprovides a cost improvement to the structural metrics and the change tothe circuit design is valid.
 17. The method of claim 16, wherein thecircuit design does not include information about the type of technologyof the circuit elements.
 18. The method of claim 16, wherein determiningthe structural metric comprises: determining a plurality of distances,wherein each distance is between each pair of the nodes; determining aneighborhood population for each distance, wherein the neighborhoodpopulation corresponds to the number of the nodes that are within thedistance; and setting the structural metric to an average of theneighborhood populations.
 19. The method of claim 16, whereindetermining the structural metric comprises: determining the minimumnumber of the edges that must be cut to separate every pair of the nodesin the graph; and setting the structural metric to the sum of theminimum number of edges for each pair.
 20. The method of claim 16,wherein determining the structural metric comprises: determining foreach pair of the nodes, a number of the nodes that are shared within apredefined distance; and setting the structural metric to sum of thenumbers.